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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CNDS - Xarxes de Computadors i Sistemes Distribuïts |
dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | García Vidal, Jorge |
dc.contributor.author | Corbal San Adrián, Jesús |
dc.contributor.author | Cerdà Alabern, Llorenç |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2003 |
dc.identifier.citation | García, J., Corbal, J., Cerdà, L., Valero, M. Design and implementation of high-performance memory systems for future packet buffers. A: Annual IEEE/ACM International Symposium on Microarchitecture. "36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003, MICRO-36: proceedings". San Diego, California: Institute of Electrical and Electronics Engineers (IEEE), 2003, p. 372-384. |
dc.identifier.citation | 0-7695-2043-X |
dc.identifier.citation | 10.1109/MICRO.2003.1253211 |
dc.identifier.uri | http://hdl.handle.net/2117/104301 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/1253211/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Routing protocols (Computer network protocols) |
dc.subject | Buffer storage |
dc.subject | Memory architecture |
dc.subject | Packet switching |
dc.subject | DRAM chips |
dc.subject | SRAM chips |
dc.subject | Encaminadors (Xarxes d'ordinadors) |
dc.title | Design and implementation of high-performance memory systems for future packet buffers |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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