ITCA: Inter-Task Conflict-Aware CPU accounting for CMPs

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RECERCAT Home > Universitat Politècnica de Catalunya > Documents de recerca > View document

To access the full text documents, please follow this link: http://hdl.handle.net/2117/105237

dc.contributor	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor	Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.contributor.author	Luque, Carlos
dc.contributor.author	Moreto Planas, Miquel
dc.contributor.author	Cazorla, Francisco
dc.contributor.author	Gioiosa, Roberto
dc.contributor.author	Buyuktosunoglu, Alper
dc.contributor.author	Valero Cortés, Mateo
dc.date	2009
dc.identifier.citation	Luque, C., Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., Valero, M. ITCA: Inter-Task Conflict-Aware CPU accounting for CMPs. A: International Conference on Parallel Architectures and Compilation Techniques. "18th International Conference on Parallel Architectures and Compilation Techniques. PACT 2009: proceedings". Raleigh, North Carolina: IEEE Computer Society, 2009, p. 203-213.
dc.identifier.citation	978-0-7695-3771-9
dc.identifier.citation	10.1109/PACT.2009.33
dc.identifier.uri	http://hdl.handle.net/2117/105237
dc.language.iso	eng
dc.publisher	IEEE Computer Society
dc.relation	http://ieeexplore.ieee.org/document/5260539/
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject	Multiprocessors
dc.subject	Cache memory
dc.subject	Parallel processing (Electronic computers)
dc.subject	Cycle accounting
dc.subject	Chip-multiProcessor
dc.subject	Cache partitioning algorithms
dc.subject	Fairness
dc.subject	ATD
dc.subject	Multiprocessadors
dc.subject	Memòria ràpida de treball (Informàtica)
dc.subject	Processament en paral·lel (Ordinadors)
dc.title	ITCA: Inter-Task Conflict-Aware CPU accounting for CMPs
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/conferenceObject
dc.description.abstract	Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism from an application. CMPs introduce complexities when accounting CPU utilization. This is due to the fact that the progress done by an application during an interval of time highly depends on the activity of the other applications it is co-scheduled with. In this paper, we identify how an inaccurate measurement of the CPU utilization affects several key aspects of the system like the application scheduling or the charging mechanism in data centers. We propose a new hardware CPU accounting mechanism to improve the accuracy when measuring the CPU utilization in CMPs and compare it with the previous accounting mechanisms. Our results show that currently known mechanisms lead to a 19 % average error when it comes to CPU utilization accounting. Our proposal reduces this error to less than 1 % in a modeled 4-core processor system.
dc.description.abstract	Peer Reviewed

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