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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.author | Corbal San Adrián, Jesús |
dc.contributor.author | Espasa Sans, Roger |
dc.contributor.author | Valero Cortés, Mateo |
dc.date | 2001 |
dc.identifier.citation | Corbal, J., Espasa, R., Valero, M. DLP+TLP processors for the next generation of media workloads. A: International Symposium on High Performance Computer Architecture. "HPCA: The Seventh International Symposium on High Performance Computer Architecture: 19-24 January 2001, Monterrey, Nuevo Leone, Mexico: proceedings". Nuevo Leone: Institute of Electrical and Electronics Engineers (IEEE), 2001, p. 219-228. |
dc.identifier.citation | 0-7695-1019-1 |
dc.identifier.citation | 10.1109/HPCA.2001.903265 |
dc.identifier.uri | http://hdl.handle.net/2117/112029 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | http://ieeexplore.ieee.org/document/903265/ |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Simultaneous multithreading processors |
dc.subject | High performance computing |
dc.subject | Performance evaluation |
dc.subject | Multi-threading |
dc.subject | Microprocessadors |
dc.subject | Càlcul intensiu (Informàtica) |
dc.title | DLP+TLP processors for the next generation of media workloads |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
dc.description.abstract | |
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