Unpredictable bits generation based on RRAM parallel configuration

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dc.contributor	Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor	Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.contributor.author	Arumi Delgado, Daniel
dc.contributor.author	Gómez Pau, Álvaro
dc.contributor.author	Manich Bou, Salvador
dc.contributor.author	Rodríguez Montañés, Rosa
dc.contributor.author	Bargalló, Mireia
dc.contributor.author	Campabadal, Francesca
dc.date	2018-12-12
dc.identifier.citation	Arumi, D. [et al.]. Unpredictable bits generation based on RRAM parallel configuration. "IEEE electron device letters", 12 Desembre 2018, vol. 40, núm. 2, p. 341-344.
dc.identifier.citation	0741-3106
dc.identifier.citation	10.1109/LED.2018.2886396
dc.identifier.uri	http://hdl.handle.net/2117/127528
dc.language.iso	eng
dc.relation	https://ieeexplore.ieee.org/document/8573799
dc.relation	info:eu-repo/grantAgreement/MICIU/2PE/TEC2017-84321-C4-1-R
dc.relation	info:eu-repo/grantAgreement/MICIU/2PE/TEC2013-41209-
dc.relation	info:eu-repo/grantAgreement/MICIU/2PE/TEC2014-54906-JIN
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Informàtica::Seguretat informàtica
dc.subject	Electrodes
dc.subject	Electric resistance
dc.subject	Computer security
dc.subject	RRAM
dc.subject	variability
dc.subject	PUF
dc.subject	hardware security
dc.subject	Elèctrodes
dc.subject	Resistència elèctrica
dc.subject	Seguretat informàtica
dc.title	Unpredictable bits generation based on RRAM parallel configuration
dc.type	info:eu-repo/semantics/submittedVersion
dc.type	info:eu-repo/semantics/article
dc.description.abstract	In this letter a cell with the parallel combination of two TiN/Ti/HfO2/W resistive random access memory (RRAM) devices is studied for the generation of unpredictable bits. Measurements confirm that a simultaneous parallel SET operation in which one of the two RRAMs switches to the low resistance state (LRS) is an unpredictable process showing random properties for different sets of cells. Furthermore, given a device pair, the same device switches during subsequent write operations. The proposed cell is also analyzed under different current compliances and pulse widths with the same persistent behavior being observed. The features of the proposed cell, which provide data obfuscation without compromising reliability, pave the way for its application in Physical Unclonable Functions (PUFs) for hardware security purposes.
dc.description.abstract	Peer Reviewed

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