From synchronous to asynchronous: an automatic approach

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To access the full text documents, please follow this link: http://hdl.handle.net/2117/130843

dc.contributor	Universitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.contributor	Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.contributor.author	Cortadella, Jordi
dc.contributor.author	Kondratyev, Alex
dc.contributor.author	Lavagno, Luciano
dc.contributor.author	Lwin, Kelvin
dc.contributor.author	Sotiriou, Christos P.
dc.date	2004
dc.identifier.citation	Cortadella, J. [et al.]. From synchronous to asynchronous: an automatic approach. A: Design, Automation and Test in Europe Conference and Exhibition. "Design, Automation and Test in Europe Conference and Exhibition: Paris, France, February 16–20, 2004". Institute of Electrical and Electronics Engineers (IEEE), 2004, p. 1368-1369.
dc.identifier.citation	0-7695-2085-5
dc.identifier.citation	10.1109/DATE.2004.1269092
dc.identifier.uri	http://hdl.handle.net/2117/130843
dc.language.iso	eng
dc.publisher	Institute of Electrical and Electronics Engineers (IEEE)
dc.relation	https://ieeexplore.ieee.org/document/1269092
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject	Asynchronous circuits
dc.subject	Logic circuits
dc.subject	Latches
dc.subject	Clocks
dc.subject	Pipelines
dc.subject	Circuit synthesis
dc.subject	Delay
dc.subject	Optimization methods
dc.subject	Design methodology
dc.subject	Network synthesis
dc.subject	Standards development
dc.subject	Circuits asíncrons
dc.subject	Circuits lògics
dc.title	From synchronous to asynchronous: an automatic approach
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/conferenceObject
dc.description.abstract	This paper presents a methodology to derive asynchronous circuits from optimized synchronous circuits by replacing the clock distribution tree by a handshaking network. A case study shows the applicability of the method and the potential benefits of de-synchronizing synchronous circuits.
dc.description.abstract	Peer Reviewed

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