The synthesis of digital circuits is a basic skill in all the bachelor programmes around the ICT area of knowledge, such as Computer Science, Telecommunication Engineering or Electrical Engineering. An important hindrance in the learning process of this skill is that the existing educational tools for the design of circuits do not allow the student to validate if his design satisfies the specification. Furthermore, an automatic feedback is essential in order to help students to fix incorrect designs. In this paper, we propose an online platform where the students can design and verify their circuits with an individual and automatic feedback. The technical aspects of the platform and the designed verification tool are presented. The impact of the platform on the learning process of the students is illustrated by analyzing the student performance on the course where the platform has been used. Results on the utilization of the platform versus the success rate and marks in the final exam are presented and compared with previous semesters.
English
digital circuit design; automatic assessment; e-learning; formal verification; model checking; diseño de circuito digital; evaluación automática; e-learning; verificación formal; control de modelo; disseny de circuits digitals; avaluació automàtica; aprenentatge virtual; verificació formal; comprovació de models; Web-based instruction; Ensenyament virtual; Enseñanza virtual
IEEE Transactions on Learning Technologies
IEEE Transactions on Learning Technologies, 2014, 7(4)
https://doi.org/10.1109/tlt.2014.2320919
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Articles [361]