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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
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dc.contributor | Universitat Politècnica de Catalunya. VIRTUOS - Virtualisation and Operating Systems |
dc.contributor.author | Lasheras Mas, Ana |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | Rodríguez Luna, Eva |
dc.contributor.author | Cassano, Luca |
dc.date | 2019 |
dc.identifier.citation | Lasheras, A. [et al.]. Protecting RSA hardware accelerators against differential fault analysis through residue checking. A: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. "2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 1-6. |
dc.identifier.citation | 978-1-7281-2260-1 |
dc.identifier.citation | 10.1109/DFT.2019.8875320 |
dc.identifier.citation | 19079069 |
dc.identifier.uri | http://hdl.handle.net/2117/175113 |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.relation | https://ieeexplore.ieee.org/document/8875320 |
dc.rights | info:eu-repo/semantics/openAccess |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Seguretat informàtica::Criptografia |
dc.subject | Public key cryptography |
dc.subject | Fault-tolerant computing |
dc.subject | Attack resistance |
dc.subject | Cryptographic hardware accelerators |
dc.subject | Differential fault analysis |
dc.subject | Hardware security |
dc.subject | Criptografia |
dc.subject | Tolerància als errors (Informàtica) |
dc.title | Protecting RSA hardware accelerators against differential fault analysis through residue checking |
dc.type | info:eu-repo/semantics/submittedVersion |
dc.type | info:eu-repo/semantics/conferenceObject |
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