A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability

Author

Li, Fan

Mawby, Philip

Song, Qiu

Perez-Tomas, Amador

Shah, Vishal

Sharma, Yogesh

Hamilton, Dean P.

Fisher, Craig

Gammon, Peter

Jennings, M. R.

Publication date

2020

Abstract

Despite the recent advances in 3C-SiC technology, there is a lack of statistical analysis on the reliability of SiO layers on 3C-SiC, which is crucial in power MOS device developments. This article presents a comprehensive study of the medium-and long-term time-dependent dielectric breakdowns (TDDBs) of 65-nm-thick SiO layers thermally grown on a state-of-the-art 3C-SiC/Si wafer. Fowler-Nordheim (F-N) tunneling is observed above 7 MV/cm and an effective barrier height of 3.7 eV is obtained, which is the highest known for native SiO layers grown on the semiconductor substrate. The observed dependence of the oxide reliability on the gate active area suggests that the oxide quality has not reached the intrinsic level. Three failure mechanisms were identified and confirmed by both medium-and long-term results. Although two of them are likely due to extrinsic defects from material quality and fabrication steps, the one dominating the high field (>8.5 MV/cm) should be attributed to the electron impact ionization within SiO. At room temperature, the field acceleration factor is found to be ≈0.906 dec/(MV/cm) for high fields, and the projected lifetime exceeds 10 years at 4.5 MV/cm.

Document Type

Article

Language

English

Subjects and keywords

Logic gates; Silicon; Reliability; Dielectrics; MOSFET; Annealing; Substrates

Publisher

 

Related items

European Commission 720827

IEEE transactions on electron devices ; Vol. 67, Issue 1 (January 2020), p. 237-242

Rights

open access

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