Aging in CMOS RF linear power amplifiers : an experimental study

Abstract

An extensive experimental analysis of the HCI and BTI aging effects on RF linear power amplifiers (PA) is presented in this paper. Two different 2.45 GHz PA topologies have been implemented in a CMOS 65 nm technology, one based on a classical common-source (CS) and choke inductor, another one based on a complementary current-reuse (CR) circuit, both of them producing similar gain and output 1-dB compression point (P-1dB). These circuits have been stressed to produce accelerated aging degradation, by applying increasing supply (VDD) voltages, or increasing RF input powers (PIN). The degradation on the transistor parameters (threshold voltage and mobility), DC bias point (IDC current) and RF performance (gain, matching, compression point) have been simultaneously measured. This has allowed to observe how the reduced transistor degradation in CR PA results in a higher robustness in its RF parameters, compared to CS PA circuit. The equivalent RMS voltages have been proposed as an observable metric to assess the combined DC+RF stress in a PA circuit. This has been applied to a semi-analytical model, thus providing comprehension of the link between the conditions under which a circuit is operated, the degradation of the transistor parameters, and the effects on the DC current and RF performance.