dc.contributor
Universitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.contributor
Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.contributor.author
Machado, Lucas
dc.contributor.author
Roca Pérez, Antoni
dc.contributor.author
Cortadella, Jordi
dc.identifier
Machado, L., Roca, A., Cortadella, J. Voltage noise analysis with ring oscillator clocks. A: IEEE Computer Society Annual Symposium on VLSI. "2017 IEEE Computer Society Annual Symposium on VLSI: ISVLSI 2017: 3-5 July 2017, Bochum, North Rhine-Westfalia, Germany: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 1-6.
dc.identifier
978-1-5090-6762-6
dc.identifier
https://hdl.handle.net/2117/114876
dc.identifier
10.1109/ISVLSI.2017.11
dc.description.abstract
Voltage noise is the main source of dynamic variability in integrated circuits and a major concern for the design of Power Delivery Networks (PDNs). Ring Oscillators Clocks (ROCs) have been proposed as an alternative to mitigate the negative effects of voltage noise as technology scales down and power density increases. However, their effectiveness highly depends on the design parameters of the PDN, power consumption patterns of the system and spatial locality of the ROCs within the clock domains. This paper analyzes the impact of the PDN parameters and ROC location on the robustness to voltage noise. The capability of reacting instantaneously to unpredictable voltage droops makes ROCs an attractive solution, which allows to reduce the amount of decoupling capacitance without downgrading performance. Tolerance to voltage noise and related benefits can be increased by using multiple ROCs and reducing the size of the clock domains. The analysis shows that up to 83% of the margins for voltage noise and up to 27% of the leakage power can be reduced by using local ROCs.
dc.description.abstract
Peer Reviewed
dc.description.abstract
Postprint (author's final draft)
dc.format
application/pdf
dc.publisher
Institute of Electrical and Electronics Engineers (IEEE)
dc.relation
http://ieeexplore.ieee.org/document/7987486/
dc.subject
Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
dc.subject
Integrated circuits
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Oscillators, Electric
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Ring oscillators
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Adaptive clocking
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Circuits integrats
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Oscil·ladors elèctrics
dc.title
Voltage noise analysis with ring oscillator clocks
dc.type
Conference report
