RTL design and implementation of a framebuffer for a RISC-V processor

Abstract

El conjunt d'instruccions o ISA (de l'anglès instruction set architecture) RISC-V i la fundació que el recolza segueixen creixent ràpidament com una alternativa open-source per als dissenys hardware. Tot i que el software open-source ja representa una part important de totes les solucions software, el hardware open-source encara està començant a expandir-se. Abans d'això, el mercat estava format íntegrament per ISAs propietàries (la gran majoria provinents dels EUA) que el controlaven. Aquest Treball de Final de Grau mostra el disseny, implementació i el testing d'un framebuffer VGA pel processador RISC-V que s'està desenvolupant en el projecte DRAC del Barcelona Supercomputing Centre. En aquest document s'expliquen els diversos passos seguits i el raonament darrera les decisions preses.

The RISC-V instruction set architecture (ISA) and the foundation that supports it continue to grow rapidly as an open-source alternative for hardware designs. Despite open-source software already being established as an important part of all the software solutions, open-source hardware has only recently begun to expand. Before that, the market was entirely made of proprietary ISAs (mostly from the US) that controlled it. This Final Degree Thesis shows the design, implementation and testing of a VGA (Video Graphics Array) framebuffer for the RISC-V processor being developed in the DRAC project by the Barcelona Supercomputing Centre. This document explains the various steps taken along the way and the reasoning behind the decisions that were taken.