dc.contributor
Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor
Moll Echeto, Francisco de Borja
dc.contributor
Alonso Casanovas, Oscar
dc.contributor.author
Aguiló Domínguez, David
dc.date.issued
2023-02-07
dc.identifier
https://hdl.handle.net/2117/386424
dc.identifier
ETSETB-230.174829
dc.description.abstract
This thesis contains the physical design for the Kameleon chip as well as for its processing cores IP. The Kameleon chip is a digital SoC containing 2 cores as well as multiple accelerators developed by the DRAC partnership. Firstly, we explain our goals for the working frequencies of the finished design, as well as a description of the different IPs to be integrated within it and their functions. Then a step by step explanation of the physical designs for the Cores IP and Kameleon SoC is presented. Lastly an analysis is made of the physical designs, where we find out that we have managed to make a working design even if the frequencies that can be achieved are a bit lower than what we had hoped for.
dc.format
application/pdf
dc.publisher
Universitat Politècnica de Catalunya
dc.rights
S'autoritza la difusió de l'obra mitjançant la llicència Creative Commons o similar 'Reconeixement-NoComercial- SenseObraDerivada'
dc.subject
Systems on a chip
dc.subject
Electron accelerators
dc.subject
Integrated circuits
dc.subject
System on Chip
dc.subject
Place and Route
dc.subject
Silicon Physical Design
dc.subject
Sistemes monoxip
dc.subject
Acceleradors d'electrons
dc.subject
Circuits integrats
dc.title
Physical design of a RISC-V processor with accelerators chip in 22nm FDSOI technology
