Optimization of GPU architecture for power efficiency

Abstract

GPUs are designed to provide massive computational power to highly parallel threads. They have large register files to support this, which are also responsible for a significant portion of the GPU’s power consumption. The general trend in new GPUs released by vendors is that higher performance comes with higher power consumption. One useful metric to measure the energy efficiency of GPUs is the performance per watt (PPW), which indicates how much performance can be achieved for a single watt of power consumed. In this thesis, I propose strategies to improve this metric by tuning the occupancy and shrinking the register file size of the GPU. In GPUs, occupancy is the ratio of the number of active threads in the GPU to the maximum number of threads the hardware allows for a given time. The scheduling policies of the GPU limit the maximum number of threads possible. High occupancy generally means that threads can hide latency and thus obtain higher throughput. However, high occupancy does not always mean better performance. In this paper, I analyze the occupancy of threads in the GPU for different register file sizes for a collection of ten benchmark applications. I also quantify register file utilization and compare it to the performance and power consumption of the GPU. I show that high occupancy does not always mean better performance. The results prove that performance per watt can be improved simply by tuning the register file size, and the optimal size is significantly lower than the baseline architecture. With a reduction in the size of the register file from baseline 64KB to 40KB, we observe a power reduction of 7.13% with a performance degradation of just 1.2% on average. More improvements can be achieved with application-specific tuning of the register file size.