dc.contributor
Barcelona Supercomputing Center
dc.contributor.author
Andreu, Pablo
dc.contributor.author
Alcaide Portet, Sergi
dc.contributor.author
Lopez, Pedro
dc.contributor.author
Abella Ferrer, Jaume
dc.contributor.author
Hernandez, Carles
dc.date.issued
2025-01-02
dc.identifier
Andreu, P. [et al.]. Expanding SafeSU capabilities by leveraging security frameworks for contention monitoring in complex SoCs. «Future Generation Computer Systems», 2 Gener 2025, vol. 163, 107518.
dc.identifier
https://hdl.handle.net/2117/444947
dc.identifier
10.1016/j.future.2024.107518.
dc.description.abstract
The increased performance requirements of applications running on safety-critical systems have led to the use of complex platforms with several CPUs, GPUs, and AI accelerators. However, higher platform and system complexity challenge performance verification and validation since timing interference across tasks occurs in unobvious ways, hence defeating attempts to optimize application consolidation informedly during design phases and validating that mutual interference across tasks is within bounds during test phases. In that respect, the SafeSU has been proposed to extend inter-task interference monitoring capabilities in simple systems. However, modern mixed-criticality systems are complex, with multilayered interconnects, shared caches, and hardware accelerators. To that end, this paper proposes a non-intrusive add-on approach for monitoring interference across tasks in multilayer heterogeneous systems implemented by leveraging existing security frameworks and the SafeSU infrastructure. The feasibility of the proposed approach has been validated in an RTL RISC-V-based multicore SoC with support for AI hardware acceleration. Our results show that our approach can safely track contention and properly break down contention cycles across the different sources of interference, hence guiding optimization and validation processes.
dc.description.abstract
This work has received funding from the Chips Joint Undertaking project ISOLDE no. 101112274 and the Spanish Agencia Estatal de Investigación PCI2023-143358 grant. Pablo Andreu has received funding from Generalitat Valenciana, Spain via “Subvenciones para la contratación de personal investigador predoctoral” with reference CIACIF/2021/412. Carles Hernández is partially supported by Spanish Ministry of Science, Innovation and Universities under “Ramón Cajal”, fellowship No. RYC2020-030685-I. Funding for open access charge: CRUE-Universitat Politecnica de Valencia .
dc.description.abstract
Peer Reviewed
dc.description.abstract
Postprint (published version)
dc.format
application/pdf
dc.relation
https://www.sciencedirect.com/science/article/pii/S0167739X24004825
dc.relation
info:eu-repo/grantAgreement/EC/HE/101112274/EU/High Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems/ISOLDE
dc.relation
info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2021-2023/PCI2023-143358/ES/HIGH PERFORMANCE, SAFE, SECURE, OPEN-SOURCE LEVER-AGED RISC-V DOMAIN-SPECIFIC ECOSYSTEMS/
dc.rights
http://creativecommons.org/licenses/by/4.0/
dc.rights
Attribution 4.0 International
dc.subject
Àrees temàtiques de la UPC::Informàtica::Automàtica i control
dc.subject
Network on chip
dc.subject
Mixed-criticality
dc.title
Expanding SafeSU capabilities by leveraging security frameworks for contention monitoring in complex SoCs