dc.contributor
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor
Barcelona Supercomputing Center
dc.contributor
Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.contributor.author
Riera Villanueva, Marc
dc.contributor.author
Canal Corretger, Ramon
dc.contributor.author
Abella Ferrer, Jaume
dc.contributor.author
González Colás, Antonio María
dc.identifier
Riera, M., Canal, R., Abella, J., Gonzalez, A. A detailed methodology to compute soft error rates in advanced technologies. A: Design, Automation & Test in Europe Conference & Exhibition. "Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE): 14-18 March 2016, ICC, Dresden, Germany". Dresden: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 217-222.
dc.identifier
978-3-9815370-6-2
dc.identifier
https://hdl.handle.net/2117/98176
dc.description.abstract
System reliability has become a key design aspect for computer systems due to the aggressive technology miniaturization. Errors are typically dominated by transient faults due to radiation and are strongly related to the technology used to build hardware. However, there is a lack of detailed methodologies to model and fairly compare Soft Error Rates (SER) across different advanced technologies. This work first describes a common methodology that from (1) technology models, (2) location (latitude, longitude and altitude), (3) operating conditions and (4) circuit descriptions (i.e. SRAM, latches, logic gates) can obtain accurate Soft Error Rates. Then, we use it to characterize soft errors through current and future technologies. Results at the technology layer show that new technologies, such as
FinFET and SOI, can reduce SER up to 100x while the location can increase SER up to 650x. © 2016 EDAA.
dc.description.abstract
This work has been partially supported by the Spanish Ministry of Education and Science under grant TIN2013-44375-R and the FP7 program of the EU under contract FP7-611404 (CLERECO). Jaume Abella has been partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717.
dc.description.abstract
Peer Reviewed
dc.description.abstract
Postprint (published version)
dc.format
application/pdf
dc.publisher
Institute of Electrical and Electronics Engineers (IEEE)
dc.relation
http://ieeexplore.ieee.org/document/7459307/
dc.relation
info:eu-repo/grantAgreement/MINECO//TIN2013-44375-R/ES/MICROARQUITECTURA Y COMPILADORES PARA FUTUROS PROCESADORES III/
dc.relation
info:eu-repo/grantAgreement/EC/FP7/611404/EU/Cross-Layer Early Reliability Evaluation for the Computing cOntinuum/CLERECO
dc.relation
info:eu-repo/grantAgreement/MINECO//RYC-2013-14717/ES/RYC-2013-14717/
dc.rights
Restricted access - publisher's policy
dc.subject
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject
Àrees temàtiques de la UPC::Informàtica
dc.subject
Integrated circuits
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Software engineering
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Error correction
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Radiation hardening
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Reconfigurable hardware
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Advanced technology
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Circuit description
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Future technologies
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Operating condition
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Soft error rate
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System reliability
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Through current
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Transient faults
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Circuits integrats
dc.subject
Enginyeria de programari
dc.title
A detailed methodology to compute soft error rates in advanced technologies
dc.type
Conference report
