Título:
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Frontend frequency-voltage adaptation for optimal energy-delay/sup 2/
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Autor/a:
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Grigorios, Magklis; González González, José; González Colás, Antonio María
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Otros autores:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
Abstract:
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In this paper, we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines the benefits of both clustering and globally asynchronous locally synchronous (GALS) designs. We also present a mechanism for dynamically adapting the frequency and voltage of the frontend of the CMCD with the goal to optimize the energy-delay/sup 2/ product (ED2P). Our mechanism has minimal hardware cost, is entirely self-adjustable, does not depend on any thresholds, and achieves results close to optimal. We evaluate it on 16 SPEC 2000 applications and report 17.5% ED2P reduction on average (80% of the upper bound). |
Abstract:
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Peer Reviewed |
Materia(s):
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-Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors -Microprocessors -Frequency -Clocks -Power dissipation -Microarchitecture -Dynamic voltage scaling -Wire -Delay -Control systems -Microprocessadors |
Derechos:
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Tipo de documento:
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Artículo - Versión publicada Objeto de conferencia |
Editor:
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Institute of Electrical and Electronics Engineers (IEEE)
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