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Title:
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All-digital simple clock synthesis through a glitch-free variable-length ring oscillator
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Author:
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Pérez Puigdemont, Jordi; Moll Echeto, Francisco de Borja; Calomarde Palomino, Antonio
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. Departament d'Enginyeria de Sistemes, Automàtica i Informàtica Industrial; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
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Abstract:
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This brief presents a simple all-digital variable-length ring oscillator (VLRO) design that is capable of synchronously changing the output frequency while keeping a signal free of glitches or spurious oscillations at the frequency transitions. The correct operation of the proposed VLRO has been experimentally validated on a 90-nm Xilinx Spartan-3E field-programmable gate array, showing the ability to switch between 16 different frequencies (from 24.1 to 321 MHz for the nominal core supply voltage) under different supply voltages with the expected behavior. |
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Subject(s):
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-Àrees temàtiques de la UPC::Enginyeria electrònica
-Electric engineering
-Clocks
-digital circuits
-digital integrated circuits
-field programmable gate arrays
-ring oscillators
-semiconductor device reliability
-DELAY-LINE
-OPERATION
-DESIGN
-Enginyeria electrònica -- Aparells i accessoris |
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Rights:
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Document type:
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Article - Published version
Article |
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