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Title:
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Hardware synthesis for asynchronous communications mechanisms
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Author:
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Costa Gorgônio, Kyller; Cortadella, Jordi
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Other authors:
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Universitat Politècnica de Catalunya. Departament de Ciències de la Computació; Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
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Abstract:
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Asynchronous data communication mechanisms (ACMs) have been extensively studied as data connectors between independently timed concurrent processes. In this work an automatic method for synthesis of re-reading ACMs is introduced. This method is is oriented to the generation of hardware artifacts. The behavior of re-reading ACMs is formally defined and the correctness properties are discussed. Then it is shown how to generate the ACMs specifications and how they can be translated into a proper hardware implementation. Verilog has been used as the target language to describe the hardware being synthesized. |
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Abstract:
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Peer Reviewed |
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Subject(s):
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-Àrees temàtiques de la UPC::Informàtica::Hardware
-Verilog (Computer hardware description language)
-Formal methods (Computer science)
-Embedded computer systems
-Hardware
-Asynchronous communication
-Metastasis
-Communication system control
-Read-write memory
-Pervasive computing
-Data communication
-Connectors
-Verilog (Llenguatge de descripció de maquinari)
-Mètodes formals (Informàtica)
-Ordinadors immersos, Sistemes d' |
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Rights:
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Document type:
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Article - Published version
Conference Object |
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Published by:
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Institute of Electrical and Electronics Engineers (IEEE)
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Share:
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