Hardware synthesis for asynchronous communications mechanisms

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dc.contributor	Universitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.contributor	Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.contributor.author	Costa Gorgônio, Kyller
dc.contributor.author	Cortadella, Jordi
dc.date	2008
dc.identifier.citation	Gorgônio, K.; Cortadella, J. Hardware synthesis for asynchronous communications mechanisms. A: International Conference of the Chilean Computer Science Society. "International Conference of the Chilean Computer Science Society, SCCC 2008: 10-14 November 2008, Punta Arenas, Chile: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2008, p. 135-143.
dc.identifier.citation	978-0-7695-3403-9
dc.identifier.citation	10.1109/SCCC.2008.21
dc.identifier.uri	http://hdl.handle.net/2117/133148
dc.language.iso	eng
dc.publisher	Institute of Electrical and Electronics Engineers (IEEE)
dc.relation	https://ieeexplore.ieee.org/document/4685773
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Informàtica::Hardware
dc.subject	Verilog (Computer hardware description language)
dc.subject	Formal methods (Computer science)
dc.subject	Embedded computer systems
dc.subject	Hardware
dc.subject	Asynchronous communication
dc.subject	Metastasis
dc.subject	Communication system control
dc.subject	Read-write memory
dc.subject	Pervasive computing
dc.subject	Data communication
dc.subject	Connectors
dc.subject	Verilog (Llenguatge de descripció de maquinari)
dc.subject	Mètodes formals (Informàtica)
dc.subject	Ordinadors immersos, Sistemes d'
dc.title	Hardware synthesis for asynchronous communications mechanisms
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/conferenceObject
dc.description.abstract	Asynchronous data communication mechanisms (ACMs) have been extensively studied as data connectors between independently timed concurrent processes. In this work an automatic method for synthesis of re-reading ACMs is introduced. This method is is oriented to the generation of hardware artifacts. The behavior of re-reading ACMs is formally defined and the correctness properties are discussed. Then it is shown how to generate the ACMs specifications and how they can be translated into a proper hardware implementation. Verilog has been used as the target language to describe the hardware being synthesized.
dc.description.abstract	Peer Reviewed

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