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dc.contributor | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
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dc.contributor | Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat |
dc.contributor.author | Rodríguez Montañés, Rosa |
dc.contributor.author | Arumi Delgado, Daniel |
dc.contributor.author | Figueras Pàmies, Joan |
dc.date | 2019-07-17 |
dc.identifier.citation | Rodriguez-Montanes, R.; Arumi, D.; Figueras, J. Postbond test of through-silicon vias with resistive open defects. "IEEE transactions on very large scale integration (VLSI) systems", 17 Juliol 2019, vol. 27, núm 11, p.2596-2607 |
dc.identifier.citation | 1063-8210 |
dc.identifier.citation | 10.1109/TVLSI.2019.2925971 |
dc.identifier.uri | http://hdl.handle.net/2117/169517 |
dc.language.iso | eng |
dc.relation | https://ieeexplore.ieee.org/document/8765618 |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights | info:eu-repo/semantics/openAccess |
dc.rights | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject | Three-dimensional integrated circuits |
dc.subject | Design for testability |
dc.subject | Duty cycle (DC) |
dc.subject | Resistive open defect |
dc.subject | Three-dimensional integrated circuit (3-D IC) |
dc.subject | Through-silicon via (TSV) |
dc.subject | TSV testing. |
dc.subject | Circuits integrats tridimensionals |
dc.title | Postbond test of through-silicon vias with resistive open defects |
dc.type | info:eu-repo/semantics/publishedVersion |
dc.type | info:eu-repo/semantics/article |
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