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Title:
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HRM: Merging Hardware Event Monitors for Improved Timing Analysis of Complex MPSoCs
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Author:
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Vilardell, S.; Serra, I.; Santalla, R.; Mezzetti, E.; Abella, J.; Cazorla, F.J.
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Abstract:
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The performance monitoring unit (PMU) in multiprocessor system-on-chips (MPSoCs) is at the heart of the latest measurement-based timing analysis techniques in critical embedded systems. In particular, hardware event monitors (HEMs) in the PMU are used as building blocks in the process of budgeting and verifying software timing by tracking and controlling access counts to shared resources. While the number of HEMs in current MPSoCs reaches hundreds, they are read via performance monitoring counters whose number is usually limited to 4-8, thus requiring multiple runs of each experiment in order to collect all desired HEMs. Despite the effort of engineers in controlling the execution conditions of each experiment, the complexity of current MPSoCs makes it arguably impossible to completely remove the noise affecting each run. As a result, HEMs read in different runs are subject to different variability, and hence, those HEMs captured in different runs cannot be blindly merged. In this work, we focus on the NXP T2080 platform where we observed up to 59% variability across different runs of the same experiment for some relevant HEMs (e.g., processor cycles). We develop a HEM reading and merging (HRM) approach to join reliably HEMs across different runs as a fundamental element of any measurement-based timing budgeting and verification technique. Our method builds on order statistics and the selection of an anchor HEM read in all runs to derive the most plausible combination of HEM readings that keep the distribution of each HEM and their relationship with the anchor HEM intact. © 1982-2012 IEEE. |
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Publication date:
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2020-01-01 |
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Subject(s):
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51 |
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Pages:
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12 p. |
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Document type:
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Article
Article - Published version |
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DOI:
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10.1109/TCAD.2020.3013051
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Published by:
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Institute of Electrical and Electronics Engineers Inc.
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