The lack of high-performance RINA implementations to date makes it hard to experiment with RINA as an underlay networking fabric solution for different types of networks, and to assess RINA's benefits in practice on scenarios with high traffic loads. High-performance router implementations typically require dedicated hardware support, like FPGAs or specialised ASICs. With the advance of hardware programmability during the last years, new possibilities unfold to prototype novel networking technologies. In particular, the use of P4 for programmable ASICs holds great promise for developing a RINA router. This paper details the design and part of the implementation of the first P4-based RINA interior router, which reuses the layer management components of the IRATI RINA implementation and implements the data transfer components using a P4 program. We also describe the configuration and testing of our deployment scenarios, using ancillary open-source tools such as the P4 reference test software switch (BMv2) or the P4Runtime API.