Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
2011
This paper proposes a unique hardware-software collaborative strategy to remove useless work at 16-bit data-width granularity. The underlying motivation is to design a low power execution platform by exploiting ‘narrow’ computations. The proposal uses a strictly narrow bit-wide microarchitecture (16-bit integer datapath), which realizes the goal of a low cost, low hardware complexity, low power execution engine. Software dynamically maps the 64-bit computations by translating them into an equivalent 16-bit instruction stream and optimizing them. In this paper, we propose an optimization technique, called Global Productiveness Propagation (GPP), which is a dynamic, profile-based optimization technique that infers the minimum required dataflow by pruning narrow computations that are mostprobably useless (non-productive). More precisely, GPP speculatively prunes the static backward slices of selected narrow computations: computations that result in the same value (in their respective storage location) as that at the input of the region. This speculative optimization technique is formulated around the concept of ‘narrow’ computations because the same allow a finer granularity to distinguish between useful (productive) and useless (nonproductive) work. GPP has been evaluated on an in-order narrow bit-wide execution core, achieving an average dynamic instruction stream reduction of 6.6%, while improving overall performance by 4.2%.
Peer Reviewed
Postprint (published version)
Conference report
Anglès
Àrees temàtiques de la UPC::Informàtica::Hardware; Narrow bitwide computation; Profile-guided optimization; PGO; Compilers (Computer programs); Compiladors (Programes d'ordinador)
ACM Press, NY
Restricted access - publisher's policy
E-prints [72954]