dc.contributor
Universitat Politècnica de Catalunya. Doctorat en Arquitectura de Computadors
dc.contributor
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor
Universitat Politècnica de Catalunya. CBA - Sistemes de Comunicacions i Arquitectures de Banda Ampla
dc.contributor.author
Rasol, Kurdman Abdulrahman Rasol
dc.contributor.author
Domingo Pascual, Jordi
dc.identifier
Rasol, K.; Domingo, J. Joint latency and reliability-aware controller placement. A: International Conference on Information Networking. "The 35th International Conference on Information Networking (ICOIN 2021): January 13 (Wed.)-16 (Sat.), 2021, Jeju Island, Korea & virtual conference". Institute of Electrical and Electronics Engineers (IEEE), 2021, p. 197-202. ISBN 978-1-7281-9100-3. DOI 10.1109/ICOIN50884.2021.9333864.
dc.identifier
978-1-7281-9100-3
dc.identifier
https://hdl.handle.net/2117/341624
dc.identifier
10.1109/ICOIN50884.2021.9333864
dc.description.abstract
In network architectures based on Software Defined Networking (SDN) the control plane (control logic) is separated from the network data plane (forwarding plane) while traditional network routers combine both. Software Defined networks facilitates a centralized networking system where a logical controller manages the global view of the network. In this paper, we first propose a new metric on the controller placement problem (CPP) that simultaneously considers the communication latency and communication reliability both between switches and controllers and between controllers. Reliability is considered for single-link failure. We model the problem of determining the optimal controller placement to provide low latencies in the control plane traffic. The objective of this study is to minimize the average accumulated latency by jointly taking into account the latency between controller to switches and inter-controller while optimizing their placement for achieving an optimal balance simultaneously. The optimization problem is formulated as a mixed-integer linear programming (MILP) model under the constraints of latency and reliability. We evaluated the performance of our proposed metric by using the Internet2 OS3E network topology. Different from previous work, we focus on the control traffic exchanged among controllers to synchronize their shared data structure. Results demonstrate that the proposed method is promising.
dc.description.abstract
This research was supported by the Spanish Ministry of Economy and Competitiveness under contract TEC2017-90034-C2-1-R (ALLIANCE).
dc.description.abstract
Peer Reviewed
dc.description.abstract
Postprint (author's final draft)
dc.format
application/pdf
dc.publisher
Institute of Electrical and Electronics Engineers (IEEE)
dc.relation
https://ieeexplore.ieee.org/document/9333864
dc.relation
info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2013-2016/TEC2017-90034-C2-1-R/ES/DISEÑANDO UNA INFRAESTRUCTURA DE RED 5G DEFINIDA MEDIANTE CONOCIMIENTO HACIA LA PROXIMA SOCIEDAD DIGITAL/
dc.subject
Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors
dc.subject
Software-defined networking (Computer network technology)
dc.subject
Telecommunication -- Traffic -- Management
dc.subject
Control plane latency
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Multiple controller placements
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Single-link failure
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Mixed-Integer linear programming
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Xarxes definides per programari (Tecnologia de xarxes d'ordinadors)
dc.subject
Telecomunicació -- Tràfic -- Gestió
dc.title
Joint latency and reliability-aware controller placement
dc.type
Conference report
