Mont-Blanc 2020: Towards scalable and power efficient European HPC processors

Abstract

The Mont-Blanc 2020 (MB2020) project has triggered the development of the next generation industrial processor for Big Data and High Performance Computing (HPC). MB2020 is paving the way to the future low-power European processor for exascale, defining the System-on-Chip (SoC) architecture and implementing new critical building blocks to be integrated in such an SoC. In this paper, we first present an overview of the MB2020 project, then we describe our experimental infrastructure, the requirements of relevant applications, and the IP blocks developed in the project. Finally, we present our emulation-based final demonstrator and explain how it integrates within our first generation of HPC processors.

This work is supported by the European Community’s Horizon 2020 Framework Programme under the Mont-Blanc 2020 project, grant agreement n. 779877.

Peer Reviewed

Postprint (author's final draft)