Testbench development and performance bottleneck analysis of the cache coherence protocols in multiprocessor systems based on the RISC-V Lagarto architecture

Abstract

The Lagarto project constitutes the basis of some important processor designs; some tapeouts with different versions and refactors have been done by collaboration. The first integration of the processor has been done using the Lowrisc SoC, which is a functional system, but being a project also under development, it has too many bugs, some of them are known by the nature of the design, and some others have been found by doing a more intensive verification. At the end of the day, the collaboration aims to have a functional SoC with most of the integration done in-house, so it is convenient to know well the operation of the system under the characteristics and configurations that are required to have a system capable of providing computational power for HPC. Studies in recent years have evaluated that as Moore's law has reached an unprecedented limit, so multicore systems would solve the performance problem, which is why this work focuses on studying and stressing the hierarchy of the memory side of the coherence protocols. Overall our work represents a extensive study and analysis of the coherence protocols stressed by running specific testbenches in different cases. Results demonstrate that trends are as we expected, but with more detail in which areas of the system are more bottlenecks depending on the testbench and its data size.