Universitat de Barcelona
2022-02-21T15:14:05Z
2022-02-21T15:14:05Z
2021-08-01
2022-02-21T15:14:05Z
This paper presents a highly configurable 16-channel TDC ASIC designed in a commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 ps jitter, 5.6 ps linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW of power consumption per channel, and an area of 4.57 mm2 . The main contributions of this work are the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit and the capability to operate at different supply voltages and operating frequencies, thus providing a compromise between TDC resolution and power consumption. Keywords: TDC; time-to-digital converter; fast timing; PET; VLSI; ASIC; ToF; ToT; low power; frontend electronics
Article
Published version
English
Disseny de circuits electrònics; Circuits integrats; Electronic circuit design; Integrated circuits
MDPI
Reproducció del document publicat a: https://doi.org/10.3390/electronics10151816
Electronics, 2021, vol. 10, num. 15, p. 1-16
https://doi.org/10.3390/electronics10151816
cc-by (c) Mauricio, Joan et al., 2021
https://creativecommons.org/licenses/by/4.0/
