Title:
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Review on suitable eDRAM configurations for next nano-metric electronics era
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Author:
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Amat, Esteve; Canal Corretger, Ramon; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio
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Other authors:
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Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. Departament d'Enginyeria de Sistemes, Automàtica i Informàtica Industrial; Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. VIRTUOS - Virtualisation and Operating Systems; Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
Abstract:
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We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform their memory cell counterparts, we explored different technological proposals and operational regimes where it can be located.
The best memory cell performance is observed for the 3T1D-eDRAM cell when it is based on FinFET devices. Both device variability and SEU appear as key reliability issues for memory cells at sub-22nm technology node. |
Abstract:
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Peer Reviewed |
Subject(s):
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-Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats -Logic circuits -- Reliability -eDRAM -FinFET -sub-VT -SEU -Circuits lògics -- Fiabilitat |
Rights:
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Document type:
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Article - Submitted version Article |
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