|
Title:
|
Automatic generation of synchronous test patterns for asynchronous circuits
|
|
Author:
|
Roig Mansilla, Oriol; Cortadella, Jordi; Peña Basurto, Marco Antonio; Pastor Llorens, Enric
|
|
Other authors:
|
Universitat Politècnica de Catalunya. Departament de Ciències de la Computació; Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals; Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
|
Abstract:
|
This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exercised by applying synchronous test vectors, as is done by real-life testers. The main contribution of the paper is the abstraction of the circuit’s behavior as a synchronous finite state machine in such a way that similar techniques to those currently used for synchronous circuits can be safely applied for testing. Currently, the fault model being used is the input stuck-at model. Experimental results on different benchmarks show that our approach generates test vectors with high fault coverage. |
|
Abstract:
|
Peer Reviewed |
|
Subject(s):
|
-Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
-Asynchronous circuits
-Circuit testing
-Automatic test pattern generation
-Synchronous generators
-Test pattern generators
-Automatic testing
-Circuit faults
-Delay
-Design for testability
-Permission
-Circuits asíncrons |
|
Rights:
|
|
|
Document type:
|
Article - Published version
Conference Object |
|
Published by:
|
Institute of Electrical and Electronics Engineers (IEEE)
|
|
Share:
|
|
