Automatic generation of synchronous test patterns for asynchronous circuits

Home | About RECERCAT | Contact

Català | Castellano

All of RECERCAT

By Communities &
Collections By Defense Date By Authors By Titles By Subject

This Collection

By Defense Date By Authors By Titles By Subject

Statistics

View Statistics All RECERCAT

My RECERCAT

Other repositories directory

RECERCAT Home > Universitat Politècnica de Catalunya > Documents de recerca > View document

To access the full text documents, please follow this link: http://hdl.handle.net/2117/130226

dc.contributor	Universitat Politècnica de Catalunya. Departament de Ciències de la Computació
dc.contributor	Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor	Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.contributor	Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.contributor.author	Roig Mansilla, Oriol
dc.contributor.author	Cortadella, Jordi
dc.contributor.author	Peña Basurto, Marco Antonio
dc.contributor.author	Pastor Llorens, Enric
dc.date	1997
dc.identifier.citation	Roig, O. [et al.]. Automatic generation of synchronous test patterns for asynchronous circuits. A: Design Automation Conference. "Design Automation Conference, 34th DAC: Anaheim, CA, Anaheim Convention Center, June 9-13,1997: proceedings 1997". Institute of Electrical and Electronics Engineers (IEEE), 1997, p. 620-625.
dc.identifier.citation	0-7803-4093-0
dc.identifier.citation	10.1109/DAC.1997.597220
dc.identifier.uri	http://hdl.handle.net/2117/130226
dc.language.iso	eng
dc.publisher	Institute of Electrical and Electronics Engineers (IEEE)
dc.relation	https://ieeexplore.ieee.org/document/597220
dc.rights	info:eu-repo/semantics/openAccess
dc.subject	Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject	Asynchronous circuits
dc.subject	Circuit testing
dc.subject	Automatic test pattern generation
dc.subject	Synchronous generators
dc.subject	Test pattern generators
dc.subject	Automatic testing
dc.subject	Circuit faults
dc.subject	Delay
dc.subject	Design for testability
dc.subject	Permission
dc.subject	Circuits asíncrons
dc.title	Automatic generation of synchronous test patterns for asynchronous circuits
dc.type	info:eu-repo/semantics/publishedVersion
dc.type	info:eu-repo/semantics/conferenceObject
dc.description.abstract	This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exercised by applying synchronous test vectors, as is done by real-life testers. The main contribution of the paper is the abstraction of the circuit’s behavior as a synchronous finite state machine in such a way that similar techniques to those currently used for synchronous circuits can be safely applied for testing. Currently, the fault model being used is the input stuck-at model. Experimental results on different benchmarks show that our approach generates test vectors with high fault coverage.
dc.description.abstract	Peer Reviewed

Show simple item record

All of RECERCAT

This Collection

Statistics

My RECERCAT

Related documents

Other documents of the same author